Layout Design Developer Jobs

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Today

EDA Tools Software Engineer

Intel Hillsboro, OR

Hillsboro, OR

Today

$96k - $182k/yr Full time Backend Developer Cad Software Data Analysis

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Job Description

Intel’s PTD Litho Frame Automation Team (FRAT) within LTD (Logic Technology Development) supports fundamental process development for VLSI layout and tape-in collateral. In this on-site role in Hillsboro, you will help define process design rules, build and validate Tape-in Collaterals, and support CAD and software tooling across Intel process technology nodes.

Responsibilities

Verify VLSI layout adherence to complex layout design rules, including ownership in Quality Assurance of FRAT designs across all Intel process nodes.
Troubleshoot design and PDK (Process Design Kit) verification issues within complex physical design flows, using both industry standard and Intel tools and flows.
Write and update software code for cell design and testcases, along with verification and package design content for distribution.
Develop and support CAD design activities for the LTD Tape-in Collateral Library across ALL Intel Process Technology nodes, including CR experimental Path Finding projects.
Collaborate on, direct, extract, execute, and construct designs that will be used for process implementation, monitoring, improvement, and development ahead of other LTD efforts.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus 6+ months of hands-on experience in the domain. Experience may be demonstrated through internships, academic projects, coursework, or hands-on training.
OR Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with no prior professional experience.
Hands-on experience includes background in VLSI design or CAD, programming in Python or C++, and knowledge of Semiconductor Device Physics or basic electrical circuit theory, as well as silicon manufacturing flows.

Technologies

Python, C++
UNIX/Linux
Cadence Virtuoso, Klayout
Calibre DRV, Calibre
DRC, ICV, IC Validator

Preferred Qualifications

Familiarity with semiconductor processing/engineering or computer science (from coursework or internship or work experience).
VLSI circuit mask design layout and/or verification (from coursework or internship or work experience).
Basic solid-state physics, optics, and IC (Integrated Circuit) process flow (from coursework or internship or work experience).
Programming skills in a high-level programming language (from coursework or internship or work experience).
Familiarity with UNIX/Linux platforms (from coursework or internship or work experience).
Experience with Cadence Virtuoso, Klayout, and tools such as Calibre DRV or Calibre.
Knowledge of design rule checks (DRC), ICV, or IC Validator software tools.
Experience with custom design and verification tools, debugging, and flow development.
Strong communication and collaboration skills for cross-functional teamwork.
Proactive mindset with focus on continuous improvement and learning.

Compensation & Benefits

Salary: USD 95,640 - 181,940 per year.

Competitive pay
Stock bonuses
Health
Retirement
Vacation

Job Details

Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro
Work Model: On-site

Compliance & Hiring Practices

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. Intel does not charge fees during the hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If asked to pay any fees during hiring, report it immediately to your recruiter.

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