Mixed Signal-ASIC CAD Methodology Developer

Location: San Francisco, CA (onsite). Salary: USD 88,800 - 187,740 per year.

Capgemini offers a role focused on shaping and advancing Mixed Signal-ASIC CAD/EDA methodologies, partnering with design, layout, and physical implementation teams to refine tools, flows, and signoff practices that influence silicon quality and time-to-market.

Benefits

• Paid time off, including vacation, holidays, personal days, and sick leave
• Medical, dental, and vision coverage
• Retirement savings plans
• Life and disability insurance
• Employee assistance programs
• Additional benefits as provided by local policy and eligibility

Responsibilities

• Influence and evolve ASIC / SoC CAD tools, flows, and design methodologies across design construction, optimization, and sign-off
• Support block-level and full-chip integration, enabling high-quality, production-ready layouts
• Drive sign-off closure, including timing (SI and OCV), power, IR, and physical verification at block and chip level
• Interpret and resolve DRC, LVS, ERC, and PEX results efficiently to meet program schedules
• Apply strong knowledge of constraints, timing fixes, and SI prevention techniques
• Partner with design and layout teams to meet performance, area, power, and reliability targets
• Leverage design automation, scripting, and UNIX environments to improve flow robustness and productivity

Requirements

• 8+ years of experience in analog and mixed-signal layout design using deep submicron CMOS technologies, including 3+ years of recent work on advanced nodes such as FinFET
• Strong understanding of Mixed Signal- ASIC/SOC CAD flows and signoff methodologies, including timing, power, IR, and physical verification
• Proficient in SKILL and Perl, with a solid foundation in software development
• Python experience is a plus
• Hands-on experience with EM/IR analysis, DRC/LVS/PEX/ERC, and working through signoff and waiver processes
• Familiar with circuit design fundamentals, including device characteristics, SPICE and Verilog netlists, and simulation concepts
• Experience using industry-standard EDA tools such as Synopsys ICC/ICC2 and Cadence Innovus/Virtuoso in UNIX/Linux environments
• Strong communication and collaboration skills to work effectively across engineering disciplines and influence technical outcomes