Vivado

Vivado Developer Jobs

2 jobs found

24d ago

Principal Software Engineer

CACI Melbourne, FL

Melbourne, FL

24d ago

$100k - $220k/yr Full time Senior Design Engineering Digital Signal Processing

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Job Description

Location

Melbourne, FL (onsite)

Salary

USD 99,800 - 219,600 per year

Responsibilities

Design, implement, and optimize DSP routines for RF tasks such as modulation/demodulation, filtering, FFT processing, channelization, and digital down/up conversion.
Develop and maintain embedded Linux applications using PetaLinux on Xilinx SoC platforms.
Integrate embedded software with FPGA logic via AXI, DMA channels, interrupts, EMIO, and memory-mapped peripherals.
Interface with RF front-end components including attenuators, PLLs and frequency synthesizers, programmable gain amplifiers, and up/downconverters.
Work with high-speed RF ADC/DAC devices and manage JESD204 data paths for signal processing.
Implement and debug SPI, I2C, GPIO, and register-level control interfaces.
Support JESD204 (A/B/C) link bring-up in coordination with FPGA and hardware teams.
Conduct system bring-up, debugging, calibration, and performance optimization.
Collaborate with RF, FPGA, hardware, and systems engineers on architecture and requirements.
Validate designs using RF lab equipment such as spectrum analyzers, signal generators, oscilloscopes, and VNAs.
Document software, algorithms, interfaces, and test procedures.
Develop low-level firmware for board-level controls via FPGA or microcontrollers using VHDL and/or C/C++.

Requirements

Ability to obtain security clearance.
Bachelor's degree in an engineering discipline.
10+ years of electronics design experience.
Experience with RF transceivers such as Analog Devices AD936x, AD908x, or equivalents.
FPGA design experience using Vivado and/or Vitis.
Strong understanding of digital electronics and the ability to read schematics.
Familiarity with AXI interconnects, DMA engines, and high-throughput data paths.
Experience with spidev, IIO frameworks, or custom Linux drivers.
Knowledge of GNU toolchains, cross-compilation, and Yocto-based workflows.
Understanding of wireless or SDR systems (LTE, 5G, Wi-Fi, radar, or custom waveforms).

Technologies

PetaLinux, Xilinx SoC platforms
AXI, DMA, JESD204 (A/B/C)
SPI, I2C, GPIO
VHDL, C, C++
Vivado, Vitis
GNU toolchains, cross-compilation, Yocto
RF transceivers (Analog Devices AD936x, AD908x)

Benefits

Healthcare coverage
Wellness programs
Financial benefits
Retirement plans
Family support
Continuing education opportunities
Paid time off and related benefits

Optional Experience

Experience with Cadence tools and OrCad schematic design
Experience writing Interface Control Documentation or high-level design documents
Experience writing automated test code and controlling external test equipment
Familiarity with PIC microcontrollers
Knowledge of STM32 ARM microprocessors and software development
Ability to operate test equipment such as oscilloscopes and logic analyzers for debugging interfaces
GUI design experience in C# or C/C++ for PC-based control and test apps

What You Can Expect

A culture grounded in integrity and trust, with a continuous-growth mindset that supports professional development and collaboration across teams.

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3mo ago

ASIC CAD/EDA Flow/Methodology Developer

Sarum LLC Irvine, CA

Irvine, CA

3mo ago Closed

$50 - $60/hr Full time Electrical Engineering AutoCAD Automation

This position is no longer accepting applications (closed May 24, 2026).

Job Description

Sarum LLC invites an experienced ASIC CAD/EDA Flow/Methodology Developer to join our Irvine, CA team, working onsite to influence how advanced chips are designed and validated. The role focuses on building robust EDA flows, automating processes, and supporting SoC and programmable logic initiatives across design, verification, and manufacturing groups.

Location: Irvine, CA (onsite) · Salary: USD 50 - 60 per hourly

Summary: This role centers on designing and optimizing EDA flows, collaborating across design, verification, and manufacturing teams to advance SoC and programmable logic projects.