Systemverilog

Systemverilog Developer Jobs

2 jobs found

1d ago

Lead C++ Software Engineer - Palladium Emulation Platform

Cadence Design Systems San Jose, CA

San Jose, CA

1d ago

$119k - $221k/yr Full time Senior C++ Language Computer Skills

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Job Description

Cadence Design Systems seeks a Lead C++ Software Engineer to support development of the Cadence Palladium emulator compiler.

Responsibilities

Contribute to development of the emulator compiler for the Cadence Palladium emulation platform
Use creativity and problem-solving to address challenging compile-time issues
Learn and/or apply multi-threading and distributed computing techniques to tackle large-scale compile problems
Work on areas such as logic optimization, partitioning, and scheduling

Requirements

MS in engineering, computer science, or a related field with 2 years experience, or Ph.D in engineering, computer science, or a related field
Strong understanding of data structures, algorithms, and databases
Demonstrated proficiency in C++ and gdb debugging
General software development experience
Familiarity with Linux/Unix development
Exposure to build and version-control systems
Coursework in Hardware Descript Language, such as Verilog, SystemVerilog, or VHDL
Exposure to electronic design platforms

Technologies

C++
gdb
Linux/Unix
Verilog
SystemVerilog
VHDL
Build and version-control systems

Compensation

Annual salary range (California): $119,000 to $221,000
You may also be eligible to receive incentive compensation: bonus, equity, and benefits
Compensation range is a guideline and may vary based on qualifications, skill level, competencies, and work location

Benefits

Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical, dental, and vision plan options
Incentive compensation: bonus, equity, and benefits

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6mo ago

ASIC CAD/EDA Flow/Methodology Developer

Sarum LLC Irvine, CA

Irvine, CA

6mo ago Closed

$50 - $60/hr Full time Electrical Engineering AutoCAD Automation

This position is no longer accepting applications (closed May 24, 2026).

Job Description

Sarum LLC invites an experienced ASIC CAD/EDA Flow/Methodology Developer to join our Irvine, CA team, working onsite to influence how advanced chips are designed and validated. The role focuses on building robust EDA flows, automating processes, and supporting SoC and programmable logic initiatives across design, verification, and manufacturing groups.

Location: Irvine, CA (onsite) · Salary: USD 50 - 60 per hourly

Summary: This role centers on designing and optimizing EDA flows, collaborating across design, verification, and manufacturing teams to advance SoC and programmable logic projects.