Systemverilog Developer Jobs

1 job found

3mo ago

ASIC CAD/EDA Flow/Methodology Developer

Sarum LLC Irvine, CA

Irvine, CA

3mo ago Closed

$50 - $60/hr Full time Electrical Engineering AutoCAD Automation

This position is no longer accepting applications (closed May 24, 2026).

Job Description

Sarum LLC invites an experienced ASIC CAD/EDA Flow/Methodology Developer to join our Irvine, CA team, working onsite to influence how advanced chips are designed and validated. The role focuses on building robust EDA flows, automating processes, and supporting SoC and programmable logic initiatives across design, verification, and manufacturing groups.

Location: Irvine, CA (onsite) · Salary: USD 50 - 60 per hourly

Summary: This role centers on designing and optimizing EDA flows, collaborating across design, verification, and manufacturing teams to advance SoC and programmable logic projects.

Responsibilities

Create, deploy, and sustain robust ASIC CAD/EDA workflows to streamline the design and verification lifecycle.
Build automation utilities and scripts with Python, Perl, and SystemVerilog to boost efficiency and reliability.
Work with cross-functional teams to capture requirements, set schedules, and ensure timely milestones.
Streamline FPGA workflows to accelerate prototyping and validation of complex digital systems.
Perform root-cause investigations of flow or design issues and deliver practical debugging solutions.
Assist PCB integration by drafting schematics and layouts in AutoCAD or Revit, and validating electrical compatibility.
Contribute to system design specifications for SoC architectures while aligning with industry standards, including NEC regulations.
Support debugging of firmware and hardware interfaces using instruments such as oscilloscopes, ohmmeters, soldering gear, and vision inspection systems.
Engage in project scheduling to prioritize work and manage multiple initiatives concurrently.
Apply signal processing techniques alongside mechanical knowledge pertinent to SMT manufacturing processes.

Requirements

Proven track record with ASIC design flows and hands-on experience in Synopsys Design Compiler, Cadence Innovus, or Mentor Graphics suites.
Practical experience with FPGA development environments such as Xilinx Vivado and Intel Quartus.
Proficiency in scripting and programming languages including Python, Perl, MATLAB, and C++ for automation and data analysis.
Solid grounding in electrical engineering concepts, including schematic design, electrical system integration, and system design methodologies.
Experience with PCB layout tools like AutoCAD Revit or MicroStation is highly desirable.
Strong troubleshooting abilities centered on root-cause analysis for intricate firmware, hardware, or manufacturing issues.
A background in mechanical engineering or familiarity with SMT, soldering techniques, and mechanical assembly is advantageous.
Knowledge of quantum engineering concepts or vision inspection systems is beneficial but not required.
Strong project management capabilities, including scheduling to hit tight deadlines while upholding quality.

Technologies

Synopsys Design Compiler
Cadence Innovus
Mentor Graphics suites
Xilinx Vivado
Intel Quartus
Python
Perl
MATLAB
C++
SystemVerilog
AutoCAD
Revit
Oscilloscopes
Ohmmeters
Soldering equipment
Vision inspection systems

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